Computer Engineering and Technology: 17th CCF Conference, by Jianfeng Zhang, Wei Ding, Hengzhu Liu (auth.), Weixia Xu, PDF

By Jianfeng Zhang, Wei Ding, Hengzhu Liu (auth.), Weixia Xu, Liquan Xiao, Chengyi Zhang, Jinwen Li, Liyan Yu (eds.)

This booklet constitutes the refereed lawsuits of the seventeenth nationwide convention on computing device Engineering and expertise, NCCET 2013, held in Xining, China, in July 2013. The 26 papers provided have been rigorously reviewed and chosen from 234 submissions. they're geared up in topical sections named: program particular Processors; conversation structure; desktop software and software program Optimization; IC layout and try; Processor structure; expertise at the Horizon.

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Extra info for Computer Engineering and Technology: 17th CCF Conference, NCCET 2013, Xining, China, July 20-22, 2013. Revised Selected Papers

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1] However, the speed of such handler based on software system is highly influenced by the hardware that it runs on. Usually, it takes a relatively longer period of time for software-based market data feeds handler to process these data. So, pure softwarebased handler will not be a solution for the desire of low-latency. W. Xu et al. ): NCCET 2013, CCIS 396, pp. 44–52, 2013. © Springer-Verlag Berlin Heidelberg 2013 A Market Data Feeds Processing Accelerator Based on FPGA 45 As for the hardware, there are typically 3 kinds of techniques used for accelerators.

Assuming the frame is perfectly synchronized, so the main operations in receiver include: 1) Low pass filtering (LPF). 2) Symbol synchronization. 3) FFT after removing the cyclic prefixes (CP). 4) MIMO channel estimation. 5) MIMO detection. 1 Low Pass Filtering Finite impulsive response (FIR) low-pass-filter is used for waveform shaping at both transmitter and receiver. An N-point FIR filter with L taps is defined as L−1 data[n + l] ∗ cof [l] F IR out[n] = (1) l=0 Where data[n] and cof[l] are input data and filter coefficient where multiplication and accumulation (MAC) are the primary operations.

The third stage of MMAC unit implements the accumulation operation. 28 J. Wei et al. typ_sel 32 macmod_o_mul_reg E D Q 32 32 14 trg_typ_reg 5 macmod_t_reg macmod_o_mod_reg D D D E E E Q Q Q 14 5 32 step1: y  a b 64 [31:0] [64:32] product_h_reg 32 product_l_reg 32 E D Q E Multiplication Operation D Q E D Q 32 32 typ_reg_a mod_reg_a 14 E Q D 5 64 46 + 15 [46:32] 32 [31:0] + [64:32] high_reg D E Q 29 + 32 33 [31:0] 32 [31:0] 1 0 [32] [31:0] 32 low_reg mod_reg_b mulmod_reg D D D E E E Q Q Q 33 + [31:0] 32 [32] [31:0] 14 + [31:0] 32 E Q D macmod_r_high_reg 32 E 32 Q 32 D macmod_r_reg 32 E Q sign [32] 14 D typ_reg_b D E Q 5 typ_dat[4:0] sel_logic mux_sel[2:0] 3 step 2 : y1  y  2n ; y0  ymod2n step3 : y   ci y1  y0 step 4 : y1  y  2n ; y0  ymod2n step5 : y  ci y1  y0 step 6 : y  y  ci ; step 7 : if y  2n then r  y  mod 2n ; else r  y ; Modular Operation step8 : P  a  b; step9 : Q  P  ci ; step10 : if Q  2n then r  Q mod 2n ; else r  P; Accumulation Operation macmod_r_mod_reg Fig.

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