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Extra resources for Circuit Cellar (November 2004)
You can do one of three things to keep track of the column count from zero to 639 in the D region. The first solution is to use another counter that counts from zero to 639 using the same clock frequency as the horizontal sync counter, but this counter counts only when the horizontal sync counter is in region D. This solution requires an extra counter. The second solution is to subtract the offset for the B and C regions, so that 42 Issue 172 November 2004 when the horizontal sync counter reaches 140 (95 + 45), you will subtract 140 to get a zero.
0397). 79 µs, which is approximately 45 clock nization signal-timing diagram is shown complete screen scan in the top left cor- cycles. Similarly, you need 640 clock cycles (region D) for the 640 columns of in Figure 3. When inactive, both synchro- ner. It takes a total of 16,784 µs to complete one full screen scan. pixels and 20 clock cycles for region E. nization signals are at a logic 1 value. 77 µs (region B). A simply get the timing correct for the horifor each row scan is 800 clock cycles (95 + zontal and vertical sync signals and then 45 + 640 + 20).
Four such comparators are used for the four horizontal regions, each connected according to the ending count value that is to be tested. Within each region, you need to maintain the value of the horizontal sync sig- COLUMN_OUT9–0 V_SYNC_OUT Q ROLL _OVER9–0 CLK R CLEAR S Q V_DATA_ON CLK R CLEAR RESET RED_OUT RED GREEN_OUT GREEN BLUE_OUT BLUE 10 10 COLUMN_OUT ROW_OUT Figure 5—The VGA monitor controller circuit contains the following: a horizontal counter circuit for generating the horizontal sync and column count signals (a); a vertical counter circuit for generating the vertical sync and row count signals (b); a complete VGA controller circuit (c); and a logic symbol for the controller circuit (d).