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Circuit Cellar (March 2003) - download pdf or read online

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Example text

The MCS-51 architecture doesn’t provide hardware support for the process of implementing single stepping; however, Intel does suggest a method. If an enabled interrupt is activated, which is possible with software, and the current instruction is RETI, the architecture ensures that at least one instruction (of the interrupted code) is executed after the RETI and before the CPU reenters the ISR. [1] You may use this feature to implement the 8051-specific, single-step functionality. One advantage of single stepping with a breakpoint over the (MCS-51) interrupt implementation is that you can test the instruction at the PC and decide to step in or over the subroutine.

The disassembler reads the opcode byte and gets the instruction length, number, and type of the operand and mnemonic from the InsInfo[] table. In a few cases, the operand type suggested by the InsInfo[] table may not give a complete operand description. This calls for further inspection of the opcode or other operand. Some of these operands are decoded from the mnemonic information. A table is S — T — U — *Indicates optional argument Table 1— The debugger commands are single ASCII characters followed by another subcommand character (in a few cases).

The decoding of the operand and its interpretation are carried out by a UasmFetchOperand() function. All of the register operands occupy values less than seven. The # and / symbols are prefixed for an immediate operand and compliment of the bit operand, respectively. The short jump and few other bit-testing instructions encode the destination address as an 8-bit relative offset. The AJMP and LJMP instructions encode the destination address as 11-bit and 16-bit constant, respectively. The UasmFetchOperand() function decodes these encoded addresses and computes the absolute 16-bit destination address using current instruction address.

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